1. Field of the Invention
The present invention relates to a high impedance detecting circuit for detecting a high impedance of a predetermined node in a digital circuit connected to an output and the like of a logic circuit. The present invention also relates to a interface circuit capable of judging the presence/absence of circuit connection.
2. Description of the Background Art
A conventional input buffer for use in a semiconductor integrated circuit having a logic circuit as an internal circuit is described below. FIG. 33 is a logic diagram of an example of the conventional input buffer including CMOS gates. The input buffer 100 comprises in-series connected CMOS inverters 101 and 102. An input terminal of the input buffer 100 is connected to an output of a predetermined logic circuit, and an output from the input buffer 100 is applied to the internal circuit.
The input buffer 100 receives a signal IN having a waveform shown in FIG. 34A. The logical value of the input signal IN is either a high level (referred to hereinafter as `H`) which is higher than a logical threshold value V.sub.T of the input buffer 100 and lower than a power supply voltage Vdd or a low level (referred to hereinafter as `L`) which is lower than the logical threshold value V.sub.T and higher than a ground voltage GND. The input buffer 100 amplifies the input signal IN to output a digital signal OUT which oscillates between the power supply voltage Vdd and the ground voltage GND as shown in FIG. 34B.
Described above is the operation of the input buffer 100 when a circuit for driving the input buffer 100 is properly connected. If an interconnecting line cut off by a failure, for example, disconnects the input terminal of the input buffer 100 from the output of the logic circuit provided at the preceding stage, the voltage of the input terminal of the input buffer 100 is unstable. In general, the voltage of the input terminal of the input buffer 100 is determined by how leak current flows. If more leak current flows from the interconnecting line for the input terminal of the input buffer 100 to the ground, the voltage of the input terminal of the input buffer 100 reaches the ground voltage GND. If more leak current flows from the interconnecting line to the power supply, the voltage of the input terminal of the input buffer 100 reaches the power supply voltage Vdd. However, since the amount of leak is generally small, the interconnecting line itself is in a high impedance (referred to hereinafter as "High-Z") state.
To detect High-Z is significant also for digital circuits handling only binary signals in terms of maintenance of the whole device including an interface circuit. However, there have been no conventional input buffers 100 including means for detecting High-Z. If High-Z is detected, a failure in a semiconductor integrated circuit may be sensed and an appropriate action such as failure indication may be performed.
There has been a device which functions to support a multiplicity of input ports to select the number of input ports to be practically used in accordance with the number of interface cards prepared, such as a network device. FIG. 35 is a perspective view of a packet converting device 120 which is one type of such network devices.
A plurality of interface cards 124 are connected to a switch card 123 through a back plane 121. In a maximum arrangement, the interface cards are connected to all connectors 122A and 122B. However, if two interface cards 124 are sufficient, the interface cards 124 are connected only to the connectors 122A and the connectors 122B are not used.
An input terminal of the connectors 122B which are not in use in an interface circuit of the packet converting device 120 is at High-Z. Detecting whether or not the input terminal of the interface circuit of the packet converting device 120 is at High-Z provides means for indicating the number of interface cards 124 connected to the packet converting device 120.
There has been an input-output interface circuit for other semiconductor integrated circuits which is adapted to apply a termination voltage Vtt to an interconnecting line, for example, through a 50.OMEGA. resistor for high speed operation. Typical examples of such an input-output interface circuit include an ECL, and an HSTL (high speed transceiver logic).
FIG. 36 is a circuit diagram of an input interface circuit for receiving an output from the HSTL disclosed, for example, in "JEDEC STANDARD No. 8-6". In FIG. 36, the reference numeral 110 designates a digital circuit; 111 designates an internal circuit in the digital circuit; 112 designates an interface circuit in the digital circuit 110 for transmitting signals therethrough between the exterior of the digital circuit 110 and the internal circuit 111; 113 designates a connector in the interface circuit 112 for connecting an external circuit to the digital circuit 110; 114 designates a voltage terminal in the interface circuit 112 for receiving the termination voltage Vtt from the digital circuit 110; 115 designates a differential amplifier circuit having a non-inverting input terminal connected to the connector 113, an inverting input terminal connected to the voltage terminal 114, and an output terminal for outputting a signal from the connector 113 which is buffered to the internal circuit 111; and the reference character R10 designates a resistor having a resistance of 50.OMEGA. and connected between the connector 113 and the voltage terminal 114.
In such high-speed interface circuits, the connector 113 when not in use is not at High-Z as above described but is connected to the interconnecting line for providing the termination voltage Vtt through the 50.OMEGA. resistor R10. Thus, the High-Z detection does not determine as to whether or not the connector 113 is in use. It should be noted that the input to the connector 113 normally has an amplitude of about Vtt.+-.0.4 V.
The conventional digital circuit includes no High-Z detecting circuit and, accordingly, is incapable of detecting High-Z of a predetermined node in the digital circuit.
The conventional interface circuit does not have the function to detect High-Z and, hence, is incapable of judging whether or not the input terminal is in use.
Further, the conventional interface circuit having an input buffer including a differential amplifier circuit is disadvantageous in that, if the input terminal is not in use, the voltages of two input terminals of the differential amplifier circuit reach the termination voltage Vtt, which is an intermediate voltage, and are equal to each other, resulting in increased power consumption.